1. Field of the Invention
The invention relates to a method for forming a capacitor structure in an inter-polysilicon dielectric, more particularly for forming a semi-recessed capacitor structure in an inter-polysilicon dielectric.
2. Description of the Prior Art
In the prior art, first of all, as FIG. 1A, an inter-polysilicon dielectric layer 11 is deposited onto the surface of a semiconductor substrate 120. Especially, there is a cell 150 formed into the semiconductor substrate 120 already.
Consequentially, as FIG. 1B, a portion of the inter-polysilicon dielectric layer 11 is etched as an opening 180 by using the conventional dry etching. This opening 180 is a trapezoid-like structure, especially it owns the narrow lower and the wide upper structure.
Then, as FIG. 1C, the polysilicon layer 12 is deposited over the surface of the inter-polysilicon dielectric 11 and fills up the opening 180.
As the FIG. 1D, the portion of the polysilicon layer 12 is etched using the conventional dry etching to form a bottom plate of the capacitor. Here, the photoresist layer 162 is used as an etch mask. If the thin silicon nitride layer is formed on the surface of the polysilicon, the topographic effect of the silicon nitride layer will be produced, such as legend 170.
In the incubation time of the process, the thickness of nitride deposited on the oxide is thinner than the nitride deposited on the silicon. While the thickness of oxide-nitride-oxide layer is reduce, the topographic effect of the thin nitride deposition in the process will make the nitride thickness between the silicon and inter-polysilicon dielectric boundary becomes too thin, also this withstands the following wet oxidation process. At this time, grain boundary oxidation may occur at the neck of polysilicon via, which results in abnormal increment of node contact resistance.